1. Field of the Invention
The present invention is generally directed to memory, and more particularly to implementing an erase disturb on a non-volatile Static Random Access Memory (SRAM) cell.
2. The Relevant Technology
Semiconductor memory devices are widely used in the computer and electronics industries as a means for retaining digital information. A typical semiconductor memory device is comprised of a large number of memory elements, known as memory cells, that are each capable of storing a single digital bit. The memory cells are arranged into a plurality of separately addressable memory locations, each being capable of storing a predetermined number of digital data bits. All of the memory cells in the device are generally located upon a single semiconductor chip which is contacted and packaged for easy insertion into a computer system.
In a typical nvSRAM cell operation, one side of the trigate gets programmed while the other side remains erased or write inhibited. A method would be useful for disturbing the erase SONOS transistor to see the extent to which it gets programmed while maintaining the program SONOS transistor in a programmed state. In an array of 1 Mb to 4 Mb cells, there might be some tail bits, which may have their erased SONOS threshold's slightly more positive than expected and this may cause the SONOS window for the program SONOS transistor and the erase SONOS transistor to be small. A method to determine the extent of the erase SONOS transistor will be helpful to determine the SONOS window for the program SONOS transistor threshold voltage and the erase SONOS transistor threshold voltage especially on the tail bits in an array of 1 Mb to 4 Mb nvSRAM cells.
It would be advantageous to provide a method and apparatus for creating an erase disturb on a nvSRAM cell by eliminating the need to write the opposite state in the volatile portion of the nvSRAM so as to create a disturb on the erased SONOS transistor in the non-volatile portion.